Reachability Analysis Based Circuit-Level Formal Verification

This dissertation presents a novel verification technique for analog and mixed signal circuits. Analog circuits are widely used in many applications such as consumer electronics, telecommunications, medical electronics, and so on. Furthermore, in deep sub-micron design, physical effects might undermine common digital abstractions of circuit behavior. Therefore, it is necessary to develop systematic methodologies to formally verify hardware design using circuit-level models. We present a formal method for circuit-level verification. Our approach is based on translating verification problems to reachability analysis problems. It applies nonlinear ODEs to model circuit dynamics using modified Nodal analysis. Based on the mathematical model, forward reachable regions are computed from given initial states to explore all possible circuit behaviors. Analog properties are checked on all circuit states to ensure fully correctness or find a design flaw. Our specification language extends LTL logic with continuous time and values and applies Brockett annuli to specify analog signals. We also introduced probability into the specification to support practical analog properties such as metastability behavior. We developed and implemented a reachability analysis tool COHO for nonlinear, high-dimensional hybrid systems. COHO employs projectagons to represent and manipulate high-dimensional, non-convex reachable regions. COHO solves nonlinear ODEs efficiently by conservatively approximating ODEs as linear differential inclusions. COHO is robust and efficient. It uses arbitrary precision rational numbers to implement exact computation and trims projectagons to remove infeasible regions. To improve performance and reduce error, several techniques are developed, including a guess-verify strategy, hybrid computation, approximate